Job Description

• Contribute to automated design methodologies for ASIC physical design
• Perform ASIC physical design (synthesis, place-and-route), and sign-off (DRC/LVS) of mixed-signal SoCs
• Work with designers to integrate custom blocks into a digital toolflow

• MS in Electrical Engineering, Computer Engineering or relevant fields focused on chip-level digital design (RTL and physical design)

• History of assuming responsibility for a variety of technical tasks and completing projects independently
• Proficient in ASIC synthesis (RTL Compiler, Genus, Design Compiler), place-and-route (Encounter, Innovus, ICC), verification (NCSIM, VCS, ModelSim), and sign-off (DRC, LVS) tools
• Proficient in writing timing constraints and deep understanding of timing analysis
• Experience working with version control software, such as Git

• Experience integrating DFT components such as scan insertion, BIST, ATPG, etc.
• Experience working on digital designs with multiple clock domains and clock dividers
• Programming experience in Python
• Knowledge of high-speed SerDes or SerDes components

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